Gate Bias Stresses of Gate-All-Around Poly-Si TFTs With Multiple Nanowire Channels

摘要

Gate-all-around (GAA) poly-Si thin-film transistors (TFTs) with multiple nanowire channels has better performance compared with planar TFT, such as lower threshold voltage $V_{rm TH}$, smaller subthreshold swing (SS), lower minimum current $I_{ rm OFF}$, higher maximum on/off current ratio $I_{rm ON}/I_{rm OFF}$, and higher mobility. However, each nanowire has three sharp corners to obtain high local electric fields under gate bias stresses, such that GAA TFT inherently suffers from an inevitable reliability problem. The local electric fields accelerate the degradation of $V_{rm TH}$ and SS. The $V_{rm TH}$ degradation under negative gate bias stress is related to the released electron trapping in stressed gate oxide during diffusion-controlled electrochemical reaction. For GAA TFT, minimum $I_{rm OFF}$ and $I_{rm ON}/I_{rm OFF}$ ratio still maintain better characteristics due to smaller channel body. Moreover, the obvious retardation in mobility degradation was obtained for GAA TFT because the hydrogen atoms can effectively rearrange the tail states located near the band edge in the channel during gate bias stresses.