Die-Level 3-D Integration Technology for Rapid Prototyping of High-Performance Multifunctionality Hetero-Integrated Systems

摘要

We proposed a die-level 3-D integration technology for rapid prototyping of high-performance multifunctionality hetero-integrated systems. Commercially available 2-D chips with different functions and sizes could be processed and integrated in die level. To realize the die-level 3-D integration, fine-sized backside through silicon via (TSV) and novel detachable technologies are developed. In this paper, we demonstrated a prototype 3-D stacked image sensor system using the die-level 3-D integration technology. Three different functional chips of CMOS image sensor, correlated double sampling, and analog-to-digital converter, which were fabricated by different technologies, were processed to form fine-sized backside Cu TSV of 5-$mu{rm m}$ diameter and metal microbumps in die level. Each chip was sequentially stacked after evaluating the basic function to form a known-good-die 3-D stacked system. The fundamental characteristics of each functional chip were successfully evaluated in the fabricated prototype 3-D stacked image sensor system.