Performance of CMOS With Si pMOS and Asymmetric InP/InGaAs nMOS for Analog Circuit Applications

摘要

We propose a novel hybrid CMOS comprising a Si-channel pMOSFET and an asymmetric InP/InGaAs nMOSFET in the nanometer regime for analog applications. The performance of such a CMOS is evaluated in terms of voltage gain and gain-bandwidth (GBW) product at two different channel lengths (), 50 and 30 nm, using extensive device simulations. Our investigations reveal that the maximum gain of the hybrid CMOS inverter is improved by 37.5% and 92.1% for asymmetric InGaAs nMOS devices with InP drain at nm for and 8, respectively, as compared with an equally sized Si inverter having . In addition, GBW product of hybrid CMOS (HAS3) comprising asymmetric InGaAs nMOSFET with InP source and Si pMOSFET is increased by 148.1% and 260.4% at and 50 nm, respectively, for , compared with its Si counterpart. Furthermore, the HAS3 device yields the highest GBW peak, unity current gain frequency, and maximum oscillation frequency as compared with other hybrid and Si CMOS devices at and 50 nm.