Parasitic$RC$Aware Delay Corner Model for Sub-10-nm Logic Circuit Design

摘要

In this paper, we propose a new statistical corner model for the precise variation analysis of CMOS logic gate delay. The conventional corner model includes pessimism in its prediction of delay variation as a result of inadequate statistical consideration of device characteristics. Therefore, to develop an accurate delay corner model, we analytically derive corner modeling targets for device characteristics, which are statistically shrunk when considering the variation and the correlation of transistor and parasitic resistance and capacitance (RC). Then, the derived targets are obtained by multiplying the conventional corner parameters using the newly proposed corner scaling factors. Simulation results verify that the corner model fitted to the proposed targets accurately predicts the three standard deviation limits of delay variation. To implement the parasiticRCaware delay corner in compact models of the process design kit, an artificial neural network is used to model the complex relationship between the parasiticRCand the delay corner model. The delay variations predicted by the proposed model match well with the Monte Carlo simulation results at various simulation conditions, unlike the conventional corner model, which introduces pessimism.