Investigation of $RC$ Parasitics Considering Middle-of-the-Line in Si-Bulk FinFETs for Sub-14-nm Node Logic Applications

摘要

In this brief, we systematically investigated the effects of fin pitch (FP) and fin height () on parasitic resistances and capacitances to achieve the best delay, which is an adequate metric of the ac behavior of FinFETs, for Si bulk n/pFinFETs in system-on-a-chip applications. The delays were directly extracted from the fully calibrated technology computer aided design –– simulation results and quantitatively analyzed using parasitic capacitance components, including a middle-of-the line configuration up to Metal 1. When FP increased, the delay likewise increased due to greater . On the other hand, the delay mostly decreased due to greater ON-current as the increased. The delay with different power supply voltages ( and 0.75 V) was also studied to see the effect of scaling. Finally, a selective deposition was suggested to improve the delay about 13%.