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Gate current and oxide reliability in p/sup +/ poly MOS capacitors with poly-Si and poly-Ge/sub 0.3/Si/sub 0.7/ gate material

机译:具有多晶硅和多晶硅/ sub-Ge / sub 0.3 / Si / sub 0.7 /栅极材料的p / sup + /多晶硅MOS电容器的栅极电流和氧化物可靠性

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摘要

Fowler-Nordheim (FN) tunnel current and oxide reliability of PRiLOS capacitors with a p/sup +/ polycrystalline silicon (poly-Si) and polycrystalline germanium-silicon (poly-Ge/sub 0.3/Si/sub 0.7/) gate on 5.6-nm thick gate oxides have been compared. It is shown that the FN current depends on the gate material and the bias polarity. The tunneling barrier heights, /spl phi//sub B/, have been determined from FN-plots. The larger barrier height for negative bias, compared to positive bias, suggests that electron injection takes place from the valence band of the gate. This barrier height for the GeSi gate is 0.4 eV lower than for the Si gate due to the higher valence band edge position. Charge-to-breakdown (Q/sub bd/) measurements show improved oxide reliability of the GeSi gate on of PMOS capacitors with 5.6 nm thick gate oxide. We confirm that workfunction engineering in deep submicron MOS technologies using poly-GeSi gates is possible without limiting effects of the gate currents and oxide reliability.
机译:在5.6-上具有ap / sup + /多晶硅(poly-Si)和多晶硅锗(poly-Ge / sub 0.3 / Si / sub 0.7 /)门的PRiLOS电容器的Fowler-Nordheim(FN)隧道电流和氧化物可靠性已经比较了纳米厚的栅极氧化物。结果表明,FN电流取决于栅极材料和偏置极性。隧道势垒高度/ spl phi // sub B /已从FN-plots确定。与正偏压相比,负偏压的势垒高度更大,表明电子注入从栅极的价带发生。由于较高的价带边缘位置,GeSi栅极的势垒高度比Si栅极的势垒高度低0.4 eV。电荷击穿(Q / sub bd /)测量表明,具有5.6 nm厚栅极氧化物的PMOS电容器上的GeSi栅极的氧化物可靠性得到改善。我们确认,可以在不限制栅极电流和氧化物可靠性影响的情况下,使用多晶硅栅极进行深亚微米MOS技术的功函数工程设计。

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