首页> 外文会议>Electron Devices Meeting, 1999. IEDM Technical Digest. International >Minority carrier tunneling and stress-induced leakage current for p/sup +/ gate MOS capacitors with poly-Si and poly-Si/sub 0.7/Ge/sub 0.3/ gate material
【24h】

Minority carrier tunneling and stress-induced leakage current for p/sup +/ gate MOS capacitors with poly-Si and poly-Si/sub 0.7/Ge/sub 0.3/ gate material

机译:具有多晶硅和多晶硅/sub-0.7/Ge/sub 0.3 /栅极材料的p / sup + /栅极MOS电容器的少数载流子隧穿和应力引起的泄漏电流

获取原文

摘要

In this paper the I-V conduction mechanism for gate injection (-V/sub g/), Stress-Induced Leakage Current (SILC) characteristics and time-to-breakdown (t/sub bd/) of PMOS capacitors with p/sup +/-poly-Si and poly-SiGe gate material on 5.6, 4.8 and 3.1 nm oxide thickness are studied. A model based on Minority Carrier Tunneling (MCT) from the gate is proposed for the I-V and SILC characteristics at -V/sub g/ of our devices. Time-to-breakdown data are presented and discussed.
机译:本文采用p / sup + /的PMOS电容器的栅极注入(-V / sub g /),应力引起的漏电流(SILC)特性和击穿时间(t / sub bd /)的IV传导机理。研究了5.6、4.8和3.1 nm氧化膜厚度的多晶硅和多晶硅栅材料。针对来自我们设备的-V / sub g /的I-V和SILC特性,提出了一种基于门极少数载流子隧道(MCT)的模型。提出并讨论了故障时间数据。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号