Three-dimensional metal gate-high-/spl kappa/-GOI CMOSFETs on 1-poly-6-metal 0.18-/spl mu/m Si devices

摘要

We demonstrate three-dimensional (3-D) self-aligned [IrO/sub 2/-IrO/sub 2/-Hf]-LaAlO/sub 3/-Ge-on-Insulator (GOI) CMOS FETs above 0.18-/spl mu/m Si CMOS FETs for the first time. At an equivalent oxide thickness of 1.4 nm, the 3-D IrO/sub 2/-LaAlO/sub 3/-GOI p-MOSFETs and IrO/sub 2/-Hf-LaAlO/sub 3/-GOI nMOSFETs show high hole and electron mobilities of 234 and 357 cm/sup 2//Vs respectively, without depredating the underneath 0.18-/spl mu/m Si devices. The hole mobility is 2.5 times higher than the universal mobility, at 1 MV/cm effective electric field. These promising results are due to the low-temperature GOI device process, which is well-matched to the low thermal budget requirements of 3-D integration. The high-performance GOI devices and simple 3-D integration process, compatible to current very large-scale integration (VLSI) technology, should be useful for future VLSI.