PMOS Hole Mobility Enhancement Through SiGe Conductive Channel and Highly Compressive ILD- $hbox{SiN}_{x}$ Stressing Layer

摘要

In this letter, the SiGe-channel PMOS transistors integrated with a highly compressive contact-etching stop-layer (CESL) interlayer-dielectric-$hbox{SiN}_{x}$ stressing layer have been successfully fabricated. The performance improvements of devices with a gate length $(L_{g})$ of down to 40 nm were studied. For long-channel SiGe-channel PMOS, the mobility is at least $+$50% higher than that of the conventional bulk-Si PMOS. Moreover, compared to the conventional short-channel SiGe-channel devices, the highly compressive CESL stressor shows $+$32% current gain for $L_{g} = hbox{40} hbox{nm}$ PMOS with the thinnest $hbox{9}hbox{rm{AA}}$ Si-cap. Therefore, integrating the stressed CESL technique into the SiGe-channel structure is an efficient method for improving PMOS device performance.