Through-Silicon-Via Capacitance Reduction Technique to Benefit 3-D IC Performance

摘要

Through-silicon via (TSV) constitutes a key component interconnecting adjacent dies vertically to form 3-D integrated circuits. In this letter, we propose a method to exploit the TSV $C$ –$V$ behavior in a p-silicon substrate to achieve minimum TSV capacitance during 3-D circuit operation. The nature of the TSV $C$–$V$ characteristics depends both on TSV architecture and TSV manufacturing process, and both these factors should be optimized to obtain the minimum depletion capacitance in the desired operating voltage region. Measured $C$ –$V$ characteristics of the TSV demonstrate the effectiveness of the method.