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Gate-All-Around Single-Crystal-Like Poly-Si Nanowire TFTs With a Steep-Subthreshold Slope

机译:具有陡峭亚阈值斜率的全栅门类单晶多晶硅纳米线TFT

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摘要

We investigate the characteristics of single-crystal-like (SCL) poly-Si nanowire (SCL poly-Si NW) thin-film-transistors with gate-all-around (GAA) structures. The GAA SCL poly-Si NWs are prepared by a modified sidewall spacer process utilizing an amorphous silicon ( $alpha$-Si) mesa structure. The combination of the high surface-to-volume ratio of the NW and a nominal gate length of 0.25 $mu{rm m}$ lead to clear improvement in electrical performance, including a steep subthreshold swing $(90pm 15~{rm mV}/{rm dec})$, a virtual absence of drain-induced barrier lowering $(21pm 13~{rm mV/V})$, and a very high ON/OFF current ratio ${sim}{7}times 10^{7}~(V_{rm D}=1~{rm V},~{rm V}_{rm G}=3~{rm V})$.
机译:我们研究具有全栅(GAA)结构的单晶状(SCL)多晶硅纳米线(SCL多晶硅NW)薄膜晶体管的特性。 GAA SCL多晶硅NW是通过使用非晶硅(α-Si)台面结构的改良侧壁间隔工艺制备的。 NW的高表面积体积比和标称栅极长度0.25 $ mu {rm m} $的结合可明显改善电气性能,包括陡峭的亚阈值摆幅$(90pm 15〜{rm mV} / {rm dec})$,几乎没有漏极引起的势垒会降低$(21pm 13〜{rm mV / V})$,并且开/关电流比$ {sim} {7}乘以10 ^ {7}〜(V_ {rm D} = 1〜{rm V},〜{rm V} _ {rm G} = 3〜{rm V})$。

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