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The Efficacy of Metal-Interfacial Layer-Semiconductor Source/Drain Structure on Sub-10-nm n-Type Ge FinFET Performances

机译:金属界面层-半导体源极/漏极结构对低于10nm n型Ge FinFET性能的影响

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摘要

We investigate the impact of metal-interfacial layer-semiconductor source/drain (M-I-S S/D) structure with heavily doped n-type interfacial layer (n-IL) or with undoped IL on sub-10-nm n-type germanium (Ge) FinFET device performance using 3-D TCAD simulations. Compared to the metal-semiconductor S/D structure, the M-I-S S/D structures provide much lower contact resistivity. Especially, the M-I-S S/D structure with n-IL provides much lower contact resistivity, resulting in lower contact resistivity than -, specified in International Technology Roadmap for Semiconductors. In addition, we found that the M-I-S structure with n-IL remarkably suppresses the sensitivity of contact resistivity to S/D doping concentration.
机译:我们研究了重掺杂n型界面层(n-IL)或未掺杂IL的金属界面层半导体源/漏(MIS S / D)结构对低于10 nm的n型锗(Ge )使用3-D TCAD仿真的FinFET器件性能。与金属半导体S / D结构相比,M-I-S S / D结构提供低得多的接触电阻率。尤其是,具有n-IL的M-I-S S / D结构提供的接触电阻率要低得多,从而导致其接触电阻率比国际半导体技术路线图中指定的-更低。另外,我们发现具有n-IL的M-I-S结构显着抑制了接触电阻率对S / D掺杂浓度的敏感性。

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