首页> 外文期刊>Electrical Design News >Two gates and a microprocessor form digital PLL
【24h】

Two gates and a microprocessor form digital PLL

机译:两个门和一个微处理器构成数字PLL

获取原文
获取原文并翻译 | 示例

摘要

You CAN USE Microchip's low-cost PIC16F818 microprocessor and a pair of gates to construct a digital PLL that can clean noisy digital signals over a range of 4 to 40 kHz. Featuring programmable lock range, phase differential, and loop gain, the digital-PLL engine and lock detector can extract clock and data information from noisy, short-range radio signals (Figure 1). When you construct it using a QFN-packaged microprocessor and discrete single-gate logic devices, the circuit occupies a pc-board area that's approximately as large as an aspirin.
机译:您可以使用Microchip的低成本PIC16F818微处理器和一对门来构建数字PLL,该数字PLL可以清除4至40 kHz范围内的噪声数字信号。数字PLL引擎和锁定检测器具有可编程的锁定范围,相位差和环路增益,可以从嘈杂的短距离无线电信号中提取时钟和数据信息(图1)。当您使用QFN封装的微处理器和分立的单门逻辑器件构建电路时,电路占用的印刷电路板面积大约与阿司匹林一样大。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号