A Performance Prediction of Clock Generation PLLs in Digital CMOS Processes - The Efficacy of LC oscillator based PLLs

摘要

For clock generation, we generally design PLLs using ring oscillator based VCO and have hardly discussed the PLLs using LC oscillator based VCO. Because a ring oscillator based VCO is considered to be superior to a LC oscillator in terms of tunable frequency range, area and power. Recent increase in clock speed, however, requires rigid jitter performance. When we design PLLs for clock generation using a simple ring VCO, many calibration blocks are necessary to satisfy the design requirements, It is getting complicated to design PLLs and the power and the area increase. The superiority in the future of a ring oscillator based VCO to LC oscillator based VCO has not been discussed so far. This paper describes the performance comparison 1) with the measurement results using a current process, 2) with the design experiments using processes supposed in the future. The results of the performance prediction show that the appropriateness of LC oscillator based PLLs for clock generation will increase.