Low-voltage CMOS phase-locked loop (PLL) for high-performance microprocessor clock generation
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机译:低压CMOS锁相环(PLL)用于高性能微处理器时钟生成
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摘要
A PLL is implemented as a full differential circuit to improve the jitter performance and the operating voltage range. A process-compensated common-mode feedback is designed in the differential charge pump which together with loop filter of MOSFET capacitors maximizes the dynamic voltage range. A high-frequency divider capable of divide-mode change-on-flight is developed with eight divide mode programmability. A PLL start-up control circuit makes the PLL start and work under difficult conditions.
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