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Zero-delay buffer with common-mode equalizer for input and feedback differential clocks into a phase-locked loop (PLL)
Zero-delay buffer with common-mode equalizer for input and feedback differential clocks into a phase-locked loop (PLL)
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机译:具有共模均衡器的零延迟缓冲器,用于将输入和反馈差分时钟输入锁相环(PLL)
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摘要
A zero-delay clock generator has a phase-locked loop (PLL) that generates a feedback clock and receives a reference clocks. All clocks are differential and have a common-mode voltage. The common-mode voltage of an externally-generated reference clock can vary from the common-mode voltage of the internally-generated feedback clock. Differences in common-mode voltage of the reference clock and feedback clock cause delay variations resulting in static phase offsets of generated clocks. A common-mode sense and equalizer senses the common-mode voltages of the buffered reference and feedback clocks, and generates control voltages. The control voltages adjust the common-mode voltage and delay of differential buffers that receive the reference and feedback clocks. The control voltages adjust the differential buffers to match the common-mode voltages of the buffered reference and feedback clocks. The buffered clocks are then applied to a phase and frequency detector of the PLL.
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