Microprocessor and a digital signal processor including adder and multiplier circuits employing logic gates having discrete and weighted inputs

摘要

A microprocessor and digital signal processor (DSP) are provided. In one embodiment, the microprocessor includes a cache memory and an arithmetic and logic unit that contains at least one of an adder and a multiplier. In another embodiment, the DSP includes a signal input, a signal output and a signal transformation unit containing at least one of an adder and a multiplier. In each embodiment, the at least one includes: (1) a circuit for deriving a carry out bit from a carry in bit and first and second addend and augend bits that includes first, second and third threshold logic gates that generate intermediate bits based on threshold comparisons of concatenations of said carry in bit and said first and second addend and augend bits, and (2) combinatorial boolean logic that generates said carry out bit from said intermediate bits.