First-Order Performance Prediction of Cache Memory with Wafer-Level 3D Integration

摘要

DUE TO THE SPEED MISMATCH between the CPU and increasing main-memory size, on-chip memory is becoming a key determinant of microprocessor performance. On-chip L2 cache sizes of the Intel microprocessor family keep increasing; for example, (1) 256 Kbytes in the Pentium III Coppermine at 180-nm technology, (2) 512 Kbytes in the Pentium 4 Northwood at 130-nm technology, (3) 1 Mbytes in the Pentium M processor 755 at 90-nm technology, and (4) 4 Mbytes in the Conroe processor at 65-nm technology.