First-silicon validation and debug require a labor-intensive engineering effort of several months and have become the least predictable and most time-consuming part of a new 90-nm chip''s development cycle. Lack of adequate tools and automatic procedures is a big factor in this bottleneck. Other difficulties include nondeterministic operation and lack of time-specific expected values. This article presents a new approach that provides an efficient scalable solution to overcome these difficulties. The end results are a significant reduction of the silicon validation and debug time, and faster discovery and root-cause determination of integration problems, design bugs, and chip defects.
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