Enabling Timing Error Resilience for Low-Power Systolic-Array Based Deep Learning Accelerators

摘要

Hardware-accelerated learning and inference algorithms are quite popular in edge devices where predictable timing behavior and minimal energy consumption are required, while maintaining robustness to timing errors. To achieve this, dynamic voltage scaling techniques have been utilized in several accelerators. Therefore, this article presents Thundervolt, a framework allowing adaptive aggressive voltage underscaling while maintaining the robustness (reliability, predictability, performance) of such accelerators. -Theocharis Theocharides, University of Cyprus -Muhammad Shafique, Technische Universitat Wien