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Output synchronisation design for master–slave Boolean networks

机译:主从布尔网络的输出同步设计

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摘要

The output synchronisation of two deterministic Boolean networks coupled in the master–slave configuration is studied. First, under the algebraic framework of logical systems, an auxiliary system is constructed. Second, core input-state cycles are generalised and an algorithm is given to calculate these cycles. Third, based on core input-state cycles of the newly constructed auxiliary system, a necessary and sufficient existence condition is derived for a synchronising state feedback controller. Furthermore, a constructive method is provided to get feasible state feedback controllers when the existence condition obtained above is satisfied. Finally, an illustrative example is provided to verify the effectiveness and superiority of the presented results.
机译:研究了在主从配置中耦合的两个确定性布尔网络的输出同步。首先,在逻辑系统的代数框架下,构建了一个辅助系统。其次,概括了核心输入状态周期,并给出了计算这些周期的算法。第三,基于新构建的辅助系统的核心输入状态周期,为同步状态反馈控制器推导出了必要的充分存在条件。此外,提供了一种构造方法,当满足以上获得的存在条件时,可获得可行的状态反馈控制器。最后,提供了一个示例性例子来验证所提出结果的有效性和优越性。

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