ADD: Accelerator Design and Deploy - A tool for FPGA high-performance dataflow computing

摘要

Dataflow-based FPGA accelerators have become a promising alternative to deliverenergy-efficient high-performance computing. However, FPGA programming is still a challenge.This paper presents Accelerator Design and Deploy (ADD), a high-level framework to specify,to simulate, and to implement dataflow accelerators for streaming applications. The frameworkincludes an open dataflow operator library, and templates are provided to easily designnew operators. The framework also provides a high-level and an accurate simulation at circuitlevel with short execution times. Moreover, ADD provides software and hardware APIsto simplify the integration process, extending the benefits of portability from low-cost FPGAboards to high performance datacenter FPGA platforms. Our framework supports coupling withhigh-level programming languages, and it has been validated on two FPGA platforms: the Intelhigh-performance CPU-FPGA heterogeneous computing platform and an educational FPGA kit.We show that our simple approach presents competitive performance, both in time and energy,when compared to multi-core and GPU accelerators.