A novel approach to hedge and compensate the critical dimension variation of the developed-and-etched circuit patterns for yield enhancement in semiconductor manufacturing

摘要

Linewidth control is critical for yield enhancement in semiconductor manufacturing. As wafer fabrication reaching nano-technology nodes, existing approaches on advanced equipment control and advanced process control (AEC/APC) for variation control of individual processes are increasingly difficult to achieve desired process control due to shrinking process windows. This study aims to propose a novel approach to determine tool affinity to hedge the variation between the photolithography for pattern development and the etching process to effectively reduce the etching bias caused by tool misalignment In particular, the proposed approach integrates a feed-forward run-to-run (R2R) controller and the proposed mini-max regret tool dispatching rules in light of the tool characteristics of the photolithography and etching processes. To validate the proposed approach, an empirical study was conducted in a leading semiconductor company in Taiwan and the results showed practical viability of the approach.