An Efficient Technique for Leakage Current Estimation in Nanoscaled CMOS Circuits Incorporating Self-Loading Effects

摘要

With the scaling of CMOS technology, subthreshold, gate, and reverse biased junction band-to-band-tunneling leakage have increased dramatically. Together, they account for more than 25 percent of power consumption in the current generation of leading edge designs. Different sources of leakage can affect each other by interacting through resultant intermediate node voltages. This is called the loading effect. In this paper, we propose a pattern dependent steady-state leakage estimation technique that incorporates loading effect and accounts for all three major leakage components, namely the gate, band-to-band-tunneling, and subthreshold leakage and accounts for transistor stack effect. By observing a recursive relationship between gate leakage and loading effect, we further refine our leakage estimation technique by developing a compact leakage model that supports iteration over node voltages based on Newton-Raphson method. The proposed estimation technique based on the compact model improves performance and capacity over SPICE. We report a speedup of 18,000rm X over SPICE simulation on smaller circuits, where SPICE simulation is feasible. Results also show that loading effect is a significant factor in leakage and worsens with technology scaling.