Efficient and flexible hardware structures of the 128 bit CLEFIA block cipher

摘要

In this study, high-throughput and flexible hardware implementations of the CLEFIA lightweight block cipher are presented. A unified processing element is designed and shared for implementing of generalised Feistel network that computes round keys and encryption process in the two separate times. The most complex blocks in the CLEFIA algorithm are substitution boxes ($S_0$S0 and $S_1$S1). The $S_0$S0 S-box is implemented based on area-optimised combinational logic circuits. In the proposed S-box structure, the number of logic gates and critical path delay are reduced by using the simplification of computation terms. The S-box $S_1$S1 consists of three steps: a field inversion over ${opf F}_{28}$F28 and two affine transformations over ${opf F}_2$F2. The inversion operation is implemented over the composite field ${opf F}_{{{lpar 2}4par }2}$F(24)2 instead of inversion over ${opf F}_{28}$F28 which is an important factor for the reduction of area consumption. In addition, we proposed a flexible structure that can perform various configurations of CLEFIA to support variable key sizes: 128, 192 and 256 bit. Implementation results of the proposed architectures in 180 nm complementary metal-oxide-semiconductor technology for different key sizes are achieved. The results show improvements in terms of execution time, throughput and throughput/area compared with other related works.