(n+1) basing on known Tn. The schedule (how often the multiplication unit is called) can be considered as a parameter of the algorithm. The proposed architecture of the “differential” unit is efficient both in terms of speed (delay) and area (gate count)."/>
Efficient hardware implementation of tweakable block cipher
首页>
外国专利>
Efficient hardware implementation of tweakable block cipher
Efficient hardware implementation of tweakable block cipher
展开▼
机译:可调整分组密码的高效硬件实现
展开▼
页面导航
摘要
著录项
相似文献
摘要
A combination of an infrequently-called tiny multiplication unit and a “differential” unit that quickly computes T(n+1) basing on known Tn. The schedule (how often the multiplication unit is called) can be considered as a parameter of the algorithm. The proposed architecture of the “differential” unit is efficient both in terms of speed (delay) and area (gate count).
展开▼