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Stream Chaining: Exploiting Multiple Levels of Correlation in Data Prefetching

机译:流链:在数据预取中利用多个相关级别

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Data prefetching has long been an important technique to amortize the effects of the memory wall, and is likely to remain so in the current era of multi-core systems. Most prefetchers operate by identifying patterns and correlations in the miss address stream. Separating streams according to the memory access instruction that generates the misses is an effective way of filtering out spurious addresses from predictable streams. On the other hand, by localizing streams based on the memory access instructions, such prefetchers both lose the complete time sequence information of misses and can only issue prefetches for a single memory access instruction at a time.rnThis paper proposes a novel class of prefetchers based on the idea of linking various localized streams into predictable chains of missing memory access instructions such that the prefetcher can issue prefetches along multiple streams. In this way the prefetcher is not limited to prefetching deeply for a single missing memory access instruction but can instead adaptively prefetch for other memory access instructions closer in time.rnExperimental results show that the proposed prefetcher consistently achieves better performance than a state-of-the-art prefetcher - 10% on average, being only outperformed in very few cases and then by only 2%, and outperforming that prefetcher by as much as 55% - while consuming the same amount of memory bandwidth.
机译:长期以来,数据预取一直是摊销内存墙影响的一项重要技术,并且在当前的多核系统时代中很可能仍然如此。大多数预取器通过识别未命中地址流中的模式和相关性来进行操作。根据生成未命中的内存访问指令分离流是从可预测流中滤除虚假地址的有效方法。另一方面,通过基于存储器访问指令对流进行本地化,这样的预取器既会丢失未命中的完整时间序列信息,又一次只能针对单个存储器访问指令发出预取。关于将各种本地流链接到丢失的存储器访问指令的可预测链中的想法,使得预取器可以沿着多个流发出预取。以此方式,预取器不限于针对单个丢失的存储器访问指令进行深度预取,而是可以在更近的时间内针对其他存储器访问指令进行自适应预取。实验结果表明,所提出的预取器始终比当前状态更好地实现性能。先进的预取器-平均10%,仅在极少数情况下才胜出,然后仅增加2%,而该预取器的性能却高达55%-同时消耗相同数量的内存带宽。

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