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机译:在FPGA中实现的流应用程序中利用任务级和数据级并行性
Department of Electrical and Computer Engineering, University of Toronto, 10 King's College Road, Toronto, Ontario, M5S 3G4, Canada;
Department of Electrical and Computer Engineering, University of Toronto, 10 King's College Road, Toronto, Ontario, M5S 3G4, Canada;
Department of Electrical and Computer Engineering, University of Toronto, 10 King's College Road, Toronto, Ontario, M5S 3G4, Canada;
Data parallelism; task parallelism; replication; throughput; scalability; high-level synthesis; parallel reduction; field-programmable gate arrays; streaming; behavioral synthesis;
机译:利用数据级并行技术在FPGA上实现LDPC解码器和DCT的节能实现
机译:平衡任务和数据级别的并行性,以提高Intel Xeon Phi上矩阵计算的性能和能耗
机译:平衡任务和数据级别的并行性,以提高Intel Xeon Phi上矩阵计算的性能和能耗
机译:Grater:在FPGA加速中利用数据级并行性的近似工作流程
机译:为多指令流架构开发多粒度并行性。
机译:遥感应用中基于FPGA的量化神经网络混合类型实现
机译:在硬实时系统中映射流应用程序时,利用足够的并行性