Digital Background Calibration of Residue Amplifier Non-idealities in Pipelined ADCs

摘要

In this paper, a digital background calibration technique for pipelined analog-to-digital converters (ADCs) is presented to continuously mitigate the conversion errors arising from the residue amplifier imperfections. The introduced method indirectly measures the digitized residue errors based on a novel principle. In the proposed method, the digitized residue errors are measured through the probability distribution of the digitized residue and a two-level pseudorandom noise sequence. Behavioral simulations are provided for a 12-bit pipelined ADC architecture to show the effectiveness of the proposed technique. The simulation results show that the signal-to-noise and distortion ratio is improved from 42.94 to 72.85dB using the presented calibration technique. The required number of samples for convergence is approximately 5x10(6) clock cycles.