The design of large circuits to interconnect many processors withnlow number of I/O ports and short diameter has been one of the majorngoals of researchers. Unfortunately, the underlying topologies of mostnof the popular circuits have a degree of the node which is a function ofnthe network size. From the implementation viewpoint, networks withnunbounded degree of the node pose two problems. First, there is a limitnon the number of I/O channels allocated to a processor. Second, the I/Onunit of the processor modules may need to be modified as the result ofnnetwork expansion. In this paper, the design of high performancennetworks with constant degree of the node is addressed. A transformationnapplied to a circuit with a varying degree is essentially thenreplacement of each node with a topology with constant degree. Thenresulting hybrid circuit usually yields an efficient realization whilenpreserving the advantageous features of designs with unbounded degree.nNew circuits such as: star-connected cycles, pancake-connected cycles,nand bubble-sort connected cycles are introduced as examples of largencircuits with constant degree of the node. The proposed networks lendnthemselves to an efficient VLSI implementation without compromisingntheir efficiency in performing certain parallel algorithms
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