The use of the Cooley-Tukey algorithm for computing the 1-d FFTnlends itself to a particular matrix factorization which suggests directnimplementation by linearly-connected systolic arrays. Here we present annew systolic architecture that embodies this algorithm. Thisnimplementation requires a smaller number of processors and a smallernnumber of memory cells than other recent implementations, as well asnhaving all the advantages of systolic arrays. For the implementation ofnthe decimation-in-frequency case, word-serial data input allowsncontinuous real-time operation without the need of a serial-to-parallelnconversion device. No control or data stream switching is necessary.nComputer simulation of this architecture was done in the context of an1024 point DFT with a fixed point processor, and CMOS processornimplementation has started
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