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Analog-input digital phase-locked loops for precise frequency andphase demodulation

机译:模拟输入数字锁相环可实现精确的频率和相位解调

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Most conventional analog-input digital phase-locked loopsn(ADPLL's) suffer from the effect of in-loop quantization and fromnnonlinear behavior caused by the approximations inherent in practicalndigitally controlled oscillators (DCO's). The resulting errors limit thenaccuracy of ADPLL-based frequency demodulation and usually makenADPLL-based phase demodulation impractical because of severe phase-driftnproblems. This paper presents a new class of ADPLL's that areninsensitive to the deleterious effects of quantization, and do notnexhibit nonlinear behavior when implemented with practical DCO's. ThenADPLL's are well suited to applications requiring precise frequencyndemodulation, and can also be used for phase demodulation because theirnquantization error is well behaved even after discrete-time integration.nThe paper establishes an analogy between the ADPLL's and delta-sigmanmodulators, and applies existing delta-sigma modulator results tonpredict the frequency and phase demodulation accuracy of the ADPLL's. Anmechanization of the general architecture consisting of easilynimplemented components such as analog integrators, digital flip-flops,nand digital counters is then presented and analyzed
机译:大多数常规的模拟输入数字锁相环(ADPLL)受实际数字数控振荡器(DCO's)固有的近似值所引起的环路内量化和非线性行为的影响。由此产生的误差限制了基于ADPLL的频率解调的准确性,并且由于严重的相位漂移问题,通常使得基于nADPLL的相位解调不切实际。本文提出了一种新型的ADPLL,它对量化的有害影响不敏感,并且在采用实际DCO实现时也不会忽略非线性行为。那么ADPLL非常适合要求精确的频率n解调的应用,并且还可以用于相位解调,因为即使在离散时间积分之后,它们的n量化误差也会表现良好。n本文建立了ADPLL与delta-sigmanmodulator之间的类比,并应用了现有的delta-sigma调制器结果可以预测ADPLL的频率和相位解调精度。然后介绍并分析了由易于实现的组件(例如模拟积分器,数字触发器,nand数字计数器)组成的一般架构的机械化

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