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Analog-input digital phase-locked loops for precise frequency and phase demodulation

机译:模拟输入数字锁相环可实现精确的频率和相位解调

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Most conventional analog-input digital phase-locked loops (ADPLL's) suffer from the effect of in-loop quantization and from nonlinear behavior caused by the approximations inherent in practical digitally controlled oscillators (DCO's). The resulting errors limit the accuracy of ADPLL-based frequency demodulation and usually make ADPLL-based phase demodulation impractical because of severe phase-drift problems. This paper presents a new class of ADPLL's that are insensitive to the deleterious effects of quantization, and do not exhibit nonlinear behavior when implemented with practical DCO's. The ADPLL's are well suited to applications requiring precise frequency demodulation, and can also be used for phase demodulation because their quantization error is well behaved even after discrete-time integration. The paper establishes an analogy between the ADPLL's and delta-sigma modulators, and applies existing delta-sigma modulator results to predict the frequency and phase demodulation accuracy of the ADPLL's. A mechanization of the general architecture consisting of easily implemented components such as analog integrators, digital flip-flops, and digital counters is then presented and analyzed.
机译:大多数常规的模拟输入数字锁相环(ADPLL)受环路内量化的影响以及实际数字控制振荡器(DCO's)固有的近似值所引起的非线性行为。产生的误差限制了基于ADPLL的频率解调的精度,并且由于严重的相位漂移问题,通常使基于ADPLL的相位解调变得不切实际。本文提出了一种新型的ADPLL,它对量化的有害影响不敏感,并且在用实际DCO实现时不会表现出非线性行为。 ADPLL非常适合需要精确频率解调的应用,并且由于其量化误差即使在离散时间积分之后也表现良好,因此也可以用于相位解调。本文建立了ADPLL和delta-sigma调制器之间的类比,并应用现有的delta-sigma调制器结果来预测ADPLL的频率和相位解调精度。然后介绍并分析了由易于实现的组件(如模拟积分器,数字触发器和数字计数器)组成的通用体系结构的机械化。

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