Method for controlling digital fractional frequency-division phase-locked loop and phase-locked loop

摘要

A method for controlling a digital fractional frequency-division phase-locked loop and a phase-locked loop are disclosed. The phase-locked loop includes a control apparatus, a TDC, a DLF, a DCO, a DIV, and an SDM. The control apparatus performs delay processing on an active edge of a reference clock according to a frequency control word and a frequency division control word to obtain a delayed reference clock; and sends the delayed reference clock to the TDC so that the TDC performs phase discrimination processing on the delayed reference clock and a feedback clock. A control apparatus added to a phase-locked loop may perform delay processing on a reference clock according to a current frequency control word and a current frequency division control word, so that a feedback clock and a delayed reference clock have active edges that approximately correspond in time.