A new RSA cryptosystem hardware design based on Montgomery'salgorithm

摘要

In this paper, we propose a new algorithm based on Montgomery'snalgorithm to calculate modular multiplication that is the corenarithmetic operation in an RSA cryptosystem. The modified algorithmneliminates over large residue and has very short critical path delaynthat yields a very high speed processing. The new architecture based onnthis modified algorithm takes about 1.5n2 clock cycles on thenaverage to finish one n-bit RSA operation. We have implemented a 512-bitnsingle-chip RSA processor based on the modified algorithm with Compassn0.6-Μm SPDM CMOS cell library. The simulation results show that thenprocessor can operate up to 125 MHz and deliver the baud rate of 164nKbits/s on the average