A Low-Cost and Low-Power Time-to-Digital Converter Using Triple-Slope Time Stretching

摘要

In this brief, we present a time-to-digital converter (TDC) in which a single interpolator is used to improve the resolution by time stretching. The interpolator is based on a triple-slope conversion. Without slowing down the measured event, this approach extensively reduces the chip area and the corresponding power consumption, as compared with the prior arts with two parallel time interpolators. A prototype was designed and fabricated in a 0.35- $muhbox{m}$ CMOS digital process, and its core area merely occupies 0.126 $hbox{mm}^{2}$. Measurements show that our TDC achieves a resolution of 357 ps while consuming 1.22 mW with a 2.5-V supply. The dynamic range of the TDC exceeds 1.46 $muhbox{s}$. The measurement rate can achieve above 400 kS/s.