A Predetermined LMS Digital Background Calibration Technique for Pipelined ADCs

摘要

A digital background calibration technique for pipelined analog-to-digital converters (ADCs) is proposed to correct the capacitor mismatch, finite dc gain, and nonlinearity of residue amplifiers. It divides the pipelined ADC into two equal channels and changes the decision points of sub-ADCs with a pseudorandom sequence to perform the digital background calibration. The difference between the digital outputs of the channels is used to drive the least mean square (LMS) machine to correct the mentioned errors and also the mismatch between the channels. In order to speed up the error correction, an accurate estimation for the errors is identified. The estimation is done by utilizing a piecewise linear model and a slope mismatch measurement technique in the digital domain. Behavioral simulations of a 12-bit 100-MS/s split pipelined ADC show that the convergence time of the proposed LMS calibration technique is significantly reduced in comparison with the conventional LMS algorithm for the same signal-to-noise-and-distortion ratio.