Fine Lines in High Yield (Part CLXIII)

摘要

Misregistration of innerlayer features, or true position error of such features, can be a source of shorts and opens etalized z-axis connections (PTHs, buried vias, or microvias) of multilayers don't align properly with innerlayer features. There are numerous causes for the misregistration of innerlayers. A detailed listing of all these causes is given by Kelley and Christof-ferson in Reference 1. These registration variables can be grouped into circuit design related causes, base material issues, and printed circuit manufacturing related causes. Designers may specify certain dielectric and copper thicknesses, which have an effect on the dimensional stability of the multilayer. Circuit patterns will create uneven distribution of copper across the innerlayer surface, which will influence shrinkage or expansion locally.