Fine Lines in High Yield (Part CXXV): Fine Lines-Beyond the Limits of Semi-Additive Processing?

摘要

The finest circuitry in electronic packaging is found in the build-up microvia layers of IC packages. These circuits are formed by semi-additive processing (SAP, see Figure 1) which means a resist pattern is formed on top of very thin electroless copper, the circuits are then plated up, resist is stripped, and the base copper is "differential etched." This etching is done without a metal-etch resist to protect the plated copper and therefore some of the plated copper is lost as well. This means the resist pattern has to compensate for this etch-back. To form 10μm lines and spaces, the resist dimensions may be more like 8μm wide resist lines and 12μm resist spaces, because the etching of the 0.5 to 1μm thin base copper will etch-back at least 1μm from both sides of the plated line.