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The interplay of blocking properties with charge and potential redistribution in thin carbon-doped GaN on n-doped GaN layers

机译:在n掺杂GaN层上的薄碳掺杂GaN中,阻挡性质与电荷和电势重新分布之间的相互作用

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摘要

In carbon-doped GaN (GaN:C) buffers used in a GaN-on-Si technology, the buffer is embedded in between transition and channel layers. This makes the analysis of buffer properties difficult due to e.g., carrier injection from or potential drop at these adjacent layers. Here, we analyze capacitance-and current-voltage characteristics of 200-300 nm thick GaN:C ([C] = 10~(19)cm~(-3)) layers which are embedded between a top metal electrode and bottom n-doped GaN (n-GaN). Such structures allow a better potential control in GaN:C and thus determination of the band diagram quantitatively. The accumulation of negative charge (concentration up to 6 x 10~(17) cm~(-3)) with bias is observed in GaN:C at both polarities. For biases V_(appl) < +1.7 V at the top electrode, negative charges accumulate in GaN:C near to its interface with n-GaN so that GaN:C exhibits no potential drop and blocks leakage current. For V_(appl) > +1.7 V, accumulated negative charges in GaN:C raise an energy barrier of ~1.1 eV for electron injection from n-GaN to GaN:C. This causes a potential drop in GaN:C leading to a significant leakage current increase. The Fermi level pinning in GaN:C at a commonly referred acceptor at E_v + 0.7(±0.2) eV is extracted only from electrostatic considerations. The occupancy change of carbon acceptors is attributed to trapping processes where the dislocation-related conductive paths are supposed to be involved in carrier transport from the top metal electrode to the carbon defect.
机译:在GaN-on-Si技术中使用的碳掺杂GaN(GaN:C)缓冲器中,该缓冲器嵌入在过渡层和沟道层之间。由于例如来自这些相邻层的载流子注入或在这些相邻层处的电势下降,这使得对缓冲液性质的分析变得困难。在这里,我们分析了埋在顶部金属电极和底部n-之间的200-300 nm厚GaN:C([C] = 10〜(19)cm〜(-3))层的电容和电流-电压特性。掺杂的GaN(n-GaN)。这种结构可以更好地控制GaN:C中的电势,从而定量确定能带图。在两个极性的GaN:C中都观察到带有偏压的负电荷积累(浓度高达6 x 10〜(17)cm〜(-3))。对于顶部电极上的偏压V_(appl)<+1.7 V,负电荷在GaN:C中接近其与n-GaN的界面处积累,因此GaN:C不会出现电位降并阻止泄漏电流。对于V_(appl)> +1.7 V,GaN:C中累积的负电荷会增加约1.1 eV的势垒,用于将电子从n-GaN注入GaN:C。这会导致GaN:C的电位下降,从而导致漏电流显着增加。仅从静电考虑中提取在E_v + 0.7(±0.2)eV处通常称为受体的GaN:C的费米能级钉扎。碳受体的占有率变化归因于俘获过程,在该过程中,与位错相关的导电路径被认为参与了从顶部金属电极到碳缺陷的载流子传输。

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  • 来源
    《Applied Physics Letters》 |2017年第3期|032106.1-032106.5|共5页
  • 作者单位

    Institute of Solid State Electronics, TU Wien, Floragasse 7,1040 Vienna, Austria,KAI GmbH, Europastrafie 8, 9524 Villach, Austria;

    KAI GmbH, Europastrafie 8, 9524 Villach, Austria;

    Infineon Technologies Austria AG, Siemensstrafie 2, 9500 Villach, Austria;

    Infineon Technologies Austria AG, Siemensstrafie 2, 9500 Villach, Austria;

    Institute of Solid State Electronics, TU Wien, Floragasse 7,1040 Vienna, Austria;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);美国《生物学医学文摘》(MEDLINE);
  • 原文格式 PDF
  • 正文语种 eng
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  • 入库时间 2022-08-18 03:14:12

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