Vernier parallel delay-line based time-to-digital converter

摘要

This letter proposes a new parallel delay-line time-to-digital converter (TDC) architecture based on the Vernier principle. Two parallel delay-line stages with slightly different incremental step sizes are cascaded, resulting in a finer resolution compared to the traditional parallel delay line. A 2-bit TDC fabricated in a 0.18 μm CMOS technology demonstrates the principle with a time resolution of 2.5 ps and a differential nonlinearity of 0.13 LSB.