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Fully FPGA-based 3D (X,Y,t) imaging system with Cross Delay-Lines detectors and Eight-Channels High-Performance Time-to-Digital Converter

机译:基于FPGA的3D(X,Y,T)成像系统,具有交叉延迟线路检测器和八个通道高性能的时间到数字转换器

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Time resolved experiments are among the most powerful tools in physic for exploring photoelectron spectroscopy phenomena over time scales from milliseconds to picoseconds Moreover, acquisition systems with versatility and real-time computing are needed. Cross Delay-Lines detectors (CDL) are extremely suitable for these applications, since arrival time measurement is exploited to perform position detection, allowing to provide both information together. Typical architectures for acquisition systems are based on Aplication Specific Integrated Circuit (ASIC) Time-to-Digital Converters (TDCs) followed by a Field Programmable Logic Array (FPGA); fast parallel computing is combined with time precision, allowing to perform state-of-the-art time resolved experiments. Nevertheless, the limiting factor of this architecture is the absence of reconfigurability of the ASIC that strongly limits the customization respect to the requests of a specific set-up. Especially today, where the state-of-the-art TDCs implemented in FPGA, is comparable to the ASIC solutions. In 2019 Nuclear Science Symposium, we presented a fully-reconfigurable FPGA-based solution, where the TDC and the image reconstruction algorithm were hosted in two FPGAs. In particular, we focused on the 4-channel TDC that, guarantees high-performance in terms of resolution (1 ps), Full-Scale Range (200 µs), Integral Non Linearity, (4 ps over 500 ns), In this contribution, we give significant improvements in order to satisfy the aforementioned experimental experimental requests. In fact, the “pulse-to-pulse” dead-time of the TDC has been reduced from 20 ns to 7 ns, and the transmission rate between the FPGAs has been incremented from 10 to 100 Msps. Furthermore, we have increased the number of channels of the TDC from 4 to 8. This makes possible to correlate the CDL events with signals coming from other sources that can be as well Time-of-Fight or laser pulses as other CDL signals.
机译:时间解决的实验是用于探索光电子光谱现象的物理学中最强大的工具,从毫秒到PICOSeconds的时间尺度而言,需要具有多功能性和实时计算的采集系统。交叉延迟线检测器(CDL)非常适合于这些应用,因为利用到达时间测量以执行位置检测,允许将两个信息一起提供。用于采集系统的典型架构基于应用特定的集成电路(ASIC)时对数字转换器(TDC),后跟现场可编程逻辑阵列(FPGA);快速并行计算与时间精度相结合,允许执行最先进的时间解决实验。然而,这种架构的限制因素是缺乏ASIC的重新配置,强烈限制定制对特定设置的请求。特别是今天,在FPGA中实现的最先进的TDC,与ASIC解决方案相当。 2019年,核科学研讨会,我们提出了一种完全可重构的基于FPGA的解决方案,其中TDC和图像重建算法在两个FPGA中托管。特别是,我们专注于4通道TDC,在这一贡献中,在分辨率(1 ps),全尺寸范围(200μs),整体非线性(4 ps超过500 ns)方面,保证高性能,我们提供了显着的改进,以满足上述实验实验要求。实际上,TDC的“脉冲 - 脉冲”死区已经从20ns到7 ns减小,并且FPGA之间的传输速率从10到100 MSP递增。此外,我们已经增加了TDC的通道数量。这使得可以将CDL事件与来自来自其他来源的信号相关联,该信号可以与其他CDL信号一起作为较斗争或激光脉冲。

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