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HopliteBuf: Network Calculus-Based Design of FPGA NoCs with Provably Stall-Free FIFOs

机译:HopLiteBuf:基于网络微积分的FPGA NOC设计,可透明的无摊FFOS

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HopliteBuf is a deflection-free, low-cost, and high-speed FPGA overlay Network-on-chip (NoC) with stall-free buffers. It is an FPGA-friendly 2D unidirectional torus topology built on top of HopliteRT overlay NoC. The stall-free buffers in HopliteBuf are supported by static analysis tools based on network calculus that help determine worst-case FIFO occupancy bounds for a prescribed workload. We implement these FIFOs using cheap LUT SRAMs (Xilinx SRL32s and Intel MLABs) to reduce cost. HopliteBuf is a hybrid microarchiteclure that combines the performance benefits of conventional buffered NoCs by using stall-free buffers with the cost advantages of deflection-routed NoCs by retaining the lightweight unidirectional torus topology structure. We present two design variants of the HopliteBuf NoC: (1) single corner-turn FIFO (W - S) and (2) dual corner-turn FIFO (W - S + N). The single corner-turn (W - S) design is simpler and only introduces a buffering requirement for packets changing dimension from the X ring to the downhill Y ring (or West to South). The dual corner-turn variant requires two FIFOs for turning packets going downhill (W - S) as well as uphill (W - N). The dual corner-turn design overcomes the mathematical analysis challenges associated with single corner-turn designs for communication workloads with cyclic dependencies between flow traversal paths at the expense of a small increase in resource cost. Our static analysis delivers bounds that are not only better (in latency) than HopliteRT but also tighter by 2 - 3x. Across 100 randomly generated flowsets mapped to a 5x5 system size, HopliteBuf is able to route a larger fraction of these flowsets with 128-deep FIFOs, boost worst-case routing latency by approximate to 2x for mutually feasible flowsets, and support a 10% higher injection rate than HopliteRT. At 20% injection rates, HopliteRT is only able to route 1-2% of the flowsets, while HopliteBuf can deliver 40-50% sustainability. When compared to the W - S-bkp, backpressure-based router, we observe that our HopliteBuf solution offers 25-30% better feasibility at 30-40% lower LUT cost.
机译:HOPLITEBUF是一种无偏转,低成本,高速FPGA覆盖网络上芯片(NOC),无稳定缓冲器。它是一个FPGA友好的2D单向托伦拓扑,内置于Hoplitert覆盖Noc。 HopLitebuf中的无速度缓冲区由基于网络微积分的静态分析工具支持,有助于确定规定工作量的最坏情况的FIFO占用界限。我们使用廉价LUT SRAM(Xilinx SRL32和Intel MLAbs)实现这些FIFO以降低成本。 HopLiteBuf是一种混合微校长,其通过使用无稳定的缓冲器通过保留轻质单向圆环结构结构来结合常规缓冲NOCs的性能优势。我们展示了HopLiteBuf Noc的两个设计变体:(1)单个角匝FIFO(W - > S)和(2)双角匝FIFO(W - > S + N)。单个角度转(W - > S)设计更简单,仅引入从X环更换尺寸的数据包到下坡Y环(或西向南)的缓冲要求。双角转型需要两个FIFO用于转动数据包下坡(W - > S)以及上坡(W - > N)。双角匝数设计克服了与单拐角设计相关的数学分析挑战,用于在流程路径之间具有循环依赖性的通信工作负载,以牺牲资源成本的小增加。我们的静态分析提供不仅更好地(在延迟)的范围内比Hoplitert更好,而且还要更加紧张2 - 3倍。跨越100个随机生成的Flowsets映射到5x5系统大小,HopLiteBuf能够通过<128深FIFO,通过近似为2x来促使最坏情况路由延迟进行较大的差异,以实现相互可行的势力,并支持10%更高的注射率比Hoplitert。在20%的注射速率下,Hoplitert只能达到1-2%的势力,而HopLiteBuf可以提供40-50%的可持续性。与W - > S-BKP相比,基于背压的路由器,我们观察到我们的HOPLITEBUF解决方案提供25-30%的可行性,以30-40%降低降低成本。

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