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The Integration of Sub-10 nm Gate Oxide on MoS2 with Ultra Low Leakage and Enhanced Mobility

机译:超低泄漏和增强迁移率的MoS2上亚10 nm栅氧化物的集成

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摘要

The integration of ultra-thin gate oxide, especially at sub-10 nm region, is one of the principle problems in MoS2 based transistors. In this work, we demonstrate sub-10 nm uniform deposition of Al2O3 on MoS2 basal plane by applying ultra-low energy remote oxygen plasma pretreatment prior to atomic layer deposition. It is demonstrated that oxygen species in ultra-low energy plasma are physically adsorbed on MoS2 surfaces without making the flakes oxidized, and is capable of benefiting the mobility of MoS2 flake. Based on this method, top-gated MoS2 transistor with ultrathin Al2O3 dielectric is fabricated. With 6.6 nm Al2O3 as gate dielectric, the device shows gate leakage about 0.1 pA/μm2 at 4.5 MV/cm which is much lower than previous reports. Besides, the top-gated device shows great on/off ratio of over 108, subthreshold swing (SS) of 101 mV/dec and a mobility of 28 cm2/Vs. With further investigations and careful optimizations, this method can play an important role in future nanoelectronics.
机译:超薄栅氧化物的集成,特别是在10纳米以下的区域,是基于MoS2的晶体管的主要问题之一。在这项工作中,我们通过在原子层沉积之前应用超低能远程氧等离子体预处理,证明了在MoS2基面上亚10 nm的均匀沉积。已经证明,超低能等离子体中的氧物质物理吸附在MoS2表面上,而不会使薄片氧化,并且能够有利于MoS2薄片的迁移。基于此方法,制造了具有超薄Al2O3电介质的顶层栅极MoS2晶体管。以6.6 nm Al2O3作为栅极电介质,该器件在4.5 MV / cm时显示出约0.1 pA /μm 2 的栅漏,远低于以前的报道。此外,顶栅器件的导通/截止比超过10 8 ,亚阈值摆幅(SS)为101 mV / dec,迁移率为28 cm 2 / VS.经过进一步的研究和精心的优化,该方法在未来的纳米电子学中将发挥重要作用。

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