首页> 外国专利> MOS transistor with assisted-gates and ultra-shallow amp;ldquo;Psuedoamp;rdquo; source and drain extensions for ultra-large-scale integration

MOS transistor with assisted-gates and ultra-shallow amp;ldquo;Psuedoamp;rdquo; source and drain extensions for ultra-large-scale integration

机译:具有辅助门和超浅“伪”的MOS晶体管源极和漏极扩展,用于超大规模集成

摘要

A MOS transistor and a method of fabricating the same for Ultra Large Scale Integration applications includes a composite gate structure. The composite gate structure is comprised of a main gate electrode and two assisted-gate electrodes disposed adjacent to and on opposite sides of the main gate electrode via an oxide layer. Areas underneath the two assisted-gate electrodes form ultra-shallow “pseudo” source/drain extensions. As a result, these extensions have a more shallow depth so as to enhance immunity to short channel effects.
机译:用于超大规模集成应用的MOS晶体管及其制造方法包括复合栅极结构。该复合栅结构包括主栅电极和两个辅助栅电极,该两个辅助栅电极通过氧化层邻近主栅电极并在主栅电极的相对侧上设置。在两个辅助栅电极下面的区域形成超浅的“伪”。源/漏扩展。结果,这些扩展具有更浅的深度,从而增强了对短信道效应的抵抗力。

著录项

  • 公开/公告号US6312995B1

    专利类型

  • 公开/公告日2001-11-06

    原文格式PDF

  • 申请/专利权人 ADVANCED MICRO DEVICES INC.;

    申请/专利号US19990263557

  • 发明设计人 BIN YU;

    申请日1999-03-08

  • 分类号H01L213/36;

  • 国家 US

  • 入库时间 2022-08-22 01:02:55

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