32位低功耗高速乘法器设计

摘要

Using Verilog HDL hardware description language,a design of low power and high speed 32 -bit fixed -point multiplier is presented.The speed of the multiplier,by means of optimization the design of radix -4 booth algorithm,4 ∶2 compressor and the final wide bit adder,is improved.In addition,the power consumption of the circuit is significantly reduced by means of performing the design techniques of operand isolation,clock gating and other low -power.Based on SMIC's 0.18μm CMOS process model,the circuit is synthesized by Synopsys's Design Compiler tool.The result shows that the maximum delay can be reduced to 3.9ns,the frequency of the system can reach 256MHz and the power consumption is less than 37mW.%采用 Verilog HDL 硬件描述语言，设计了一个高性能、低功耗的32位定点乘法器。该乘法器通过对基4布斯算法、4∶2压缩器算法及最终加法器的优化设计，进一步提高了乘法的运算速度。另外，在设计中加入了操作数隔离、门控时钟等低功耗设计技术，从而大幅度减少了电路功耗。采用 SMIC 0．18μm CMOS 工艺，使用 Synopsys 的 Design Compiler 工具对电路进行逻辑综合。结果显示，最坏情况下的时间延迟为3．9ns，系统时钟频率可达256MHz，功耗小于37mW。