基于Verilog HDL的有限状态机的优化设计

摘要

有限状态机（FSM）在数字电路设计中的使用非常广泛,该文研究了有限状态机的优化设计方法。利用FPGA开发软件Quartus II和仿真软件ModelSim-Altera对不同方法所设计的状态机进行综合电路分析以及对仿真波形进行时序分析,找出不同状态机在电路上、仿真中以及稳定性上的优缺点。结果表明,采用两段式（Two-always）和三段式（Three-always）设计的状态机在多方面上都优于用一段式（One-always）所设计的状态机,而且采用三段式所设计的状态机在稳定性上更优于用两段式所设计的状态机。%FSM is widely used in digital circuit design.Optimization design method of FSM is introduced.Use FPGA development software Quartus II and simulation software to analyze the synthetical circuit of FSM designed by different methods and analyze the time sequence of simulation waveforms.Find out Advantages and disadvantages on circuit,simulation and stability of different FSMs.According the result,the FSM designed by Two-always method and Three-always method is better than that designed by One-always method on many aspects.And three-always FSM is better than two-always FSM on stability.