一种新颖的超低功耗CMOS低噪声放大器设计

摘要

A novel circuit topology for a CMOS low-noise amplifier(LNA)is presented in this paper.By employing a positive feedback technique at the common-source transistor of the cascade stage,the voltage gain can be enhanced.In addition,with the MOS transistors biased in the moderate inversion region,the proposed LNA circuit is well suited to operate at reduced power consumption and supply voltage conditions.Utilizing a standard 0.13μm CMOS process,a 5.8 GHz CMOS LNA has been designed.Operated at a supply voltage of 0.6 V, the LNA with the gain-boosting technique achieves a gain of 14.6 dB and a noise figure of 1.5 dB while consuming a dc power of 0.9 mW.The simulated input third-order intercept point is 8.5 dBm.%本文提出了一种新颖的CMOS低噪声放大器电路。该电路采用正反馈技术以提高电路的增益，并且将MOS晶体管偏置在反型区以取得超低的功耗。本文所设计的电路非常适合在低电压低功耗状态下工作。基于TSMC 0.13μm CMOS工艺，采用该电路结构设计实现了一款5.8 GHz的CMOS低噪声放大器。仿真结果表明：该电路在仅消耗0.9 mW的前提下，取得了14.6 dB的较高增益，噪声系数仅为1.5 dB，并且该电路的输入三阶交调点高达8.5 dBm。