一种AES算法的ASIC设计实现

摘要

为保证信息系统的安全性,基于现代集成电路设计方法,采用Chartered 0.35um CMOS工艺完成一款基于AES算法的密码芯片的ASIC设计.设计中首先完成了芯片的架构设计和模块划分,然后使用Verilog HDL完成了AES算法的描述.功能仿真结果表明该设计的加解密功能完全正确.最后使用Synopsys公司的Astro完成了芯片的物理设计.%In order to ensure the security of information systems, an ASIC implemention of AES based on Chartered 0. 35um CMOS process technology is shown. The Verilog HDL of AES algorithm is developed after the architecture design and module partition. The function simulation results demonstrate that the design works well. Finally, the physical design of the cipher chip is completed by Astro.