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【6h】Performance tradeoffs of wide-bit CMOS nanometer adder topologies with applied leakage reduction techniques.

机译宽比特CMOS纳米加法器拓扑与应用的泄漏减少技术之间的性能折衷。

【摘要】The scaling of nanometer technology has had a major impact on the power dissipation of CMOS circuits. As transistor size decreases it has become apparent that leakage power is becoming a dominant fighting force against future technology. Low Power VLSI designs have focused their efforts on finding new design methodologies to reduce leakage power consumption. This research explores leakage power trends through the testing of leakage power reduction techniques in wide-bit adder topologies. Five different leakage reduction techniques were applied to arithmetic adder circuits for five bit sizes in three technology nodes. The leakage reduction techniques that were investigated in this research are: input vector control, dual voltage threshold, transistor stacking, long channel devices, and power gating. Four different adder topologies viz. the ripple carry adder, carry select adder, carry bypass adder, and carry look-ahead adder were designed for 4-bit, 8-bit, 16-bit, 32-bit, and 64-bit addition. Each circuit was simulated using HSPICE for the 22nm, 32nm, and 45nm technology nodes. Predictive Technology Model (PTM) BSIM4 transistor models were used for all the simulations.;The results of the simulations were analyzed and evaluated against a 'standard' model with no applied leakage reduction technique. The trends in leakage power as a result of scaling and the effects of leakage techniques applied to nanometer technologies being explored by current IC designers were observed. The trade off of each applied leakage reduction technology was investigated. The overall results indicate that the use of long channel devices produced the optimized overall performance necessary for improving nanometer CMOS wide-bit adder circuits.

【摘要机译】纳米技术的规模化对CMOS电路的功耗产生了重大影响。随着晶体管尺寸的减小,很明显,泄漏功率正在成为对抗未来技术的主导力量。低功耗VLSI设计致力于寻找新的设计方法来减少泄漏功耗。这项研究通过测试宽位加法器拓扑中的泄漏功率降低技术来探索泄漏功率趋势。五个不同的泄漏减少技术已应用于算术加法器电路,用于三个技术节点中的五位大小。在这项研究中研究的减少泄漏的技术有:输入矢量控制,双电压阈值,晶体管堆叠,长沟道器件和功率门控。四种不同的加法器拓扑结构。纹波进位加法器,进位选择加法器,进位旁路加法器和进位超前加法器设计用于4位,8位,16位,32位和64位加法。每个电路均使用HSPICE在22nm,32nm和45nm技术节点上进行了仿真。预测技术模型(PTM)BSIM4晶体管模型用于所有仿真。;对仿真结果进行了分析,并根据未应用泄漏减少技术的“标准”模型进行了评估。观察到由于缩放而引起的泄漏功率的趋势以及当前的IC设计人员正在探索的泄漏技术应用于纳米技术的影响。研究了每种应用的减少泄漏技术的权衡。总体结果表明,长通道器件的使用产生了改善纳米CMOS宽位加法器电路所需的优化的总体性能。

【作者】Romo, Claudia.;

【作者单位】The University of Texas at San Antonio.;

【年(卷),期】2010(),

【年度】2010

【页码】149 p.

【总页数】149

【原文格式】PDF

【正文语种】eng

【中图分类】;

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